I. Field
The present invention relates generally to electronics circuits, and more specifically to techniques for fixing timing violations in a circuit design.
II. Background
A digital circuit design often includes a large number of sequential and combinatorial cells. A sequential cell is a circuit element that is triggered by a clock signal, e.g., a register or a latch. A combinatorial cell is a circuit element that is not triggered by a clock signal, e.g., an AND gate, an OR gate, some other type of gate, an inverter, and so on. A sequential cell typically has various timing requirements such as setup time and hold time requirements. The setup time is the amount of time a signal is required to remain stable at a data input of the sequential cell before the arrival of a clock edge. The hold time is the amount of time the signal is required to remain stable at the sequential cell input after the arrival of the clock edge.
The combinatorial cells are typically dispersed among the synchronous cells in the circuit design. The combinatorial cells introduce delays on the signals sent between the sequential cells. If the delays through the combinatorial cells are too long, then the signals may violate setup time requirements for the sequential cells. Conversely, if the delays through the combinatorial cells are too short, then the signals may violate hold time requirements. Setup and hold time violations may also be caused by clock skew, or more generally clock edge alignment. Fixing hold time violations may sometimes cause setup time violations, especially in a high-speed circuit design where setup and hold time violations are difficult to fix because a high clock rate results in less time between stages of sequential cells.
Many conventional circuit design tools are not able to effectively deal with hold time violations. For example, these tools may only add a delay buffer at either a starting point or an end point of a signal path with hold time violation. This limitation makes it difficult to fix many hold time violations without violating setup time requirements. A delay buffer inserted at a starting point or an end point to fix hold time violation for a signal path may cause setup time violation in the same signal path or another signal path.
There is therefore a need in the art for techniques to more efficiently fix hold time violations in a circuit design.